Semiconductor device and method for fabricating the same

Abstract

The semiconductor device includes an upper electrode line structure and a lower electrode line structure provided over a semiconductor substrate. The semiconductor device also includes a guard contact having a first portion and a second portion. The guard contact is disposed between the upper electrode line structure and the lower electrode line structure. The first and second portions of the guard contact have different line widths.

Claims

1 . A semiconductor device, comprising: an upper electrode line structure and a lower electrode line structure provided over a semiconductor substrate; and a guard contact having a first portion and a second portion that are disposed between the upper electrode line structure and the lower electrode line structure, the first and second portions of the guard contact having different line widths, wherein the first portion and the second portion of the guard contact are aligned to the middle of a longitudinal extension of the lower electrode line structure. 2 . The semiconductor device of claim 1 , wherein the guard contact has a plurality of the first portions and a plurality of the second portions, wherein the plurality of first portions and the plurality of second portions are alternately disposed. 3 . The semiconductor device according to claim 1 , wherein a width of the first portion is at least double a width of the second portion. 4 . A method for fabricating a semiconductor device, the method comprising: forming a lower electrode line structure over a semiconductor substrate having a lower structure; forming a guard line having a first portion and a second portion over the lower electrode structure, wherein a line width of the first portion and a line width of the second portion are different, the first portion and the second portion of the guard contact being aligned to the middle of a longitudinal extension of the lower electrode line structure; and forming an upper electrode line structure over the guard contact. 5 . The method according to claim 4 , wherein a width of the first portion is greater than a width of the second portion, the width being in a direction corresponding to a longitudinal direction of the lower electrode line structure. 6 . The method according to claim 4 , wherein a width of the first portion is at least double a width of the second portion.
CROSS-REFERENCES TO RELATED APPLICATIONS [0001] The present application claims priority to Korean patent application number 10-2005-0065784, filed on Jul. 20, 2005, which is incorporated by reference in its entirety. BACKGROUND OF THE INVENTION [0002] The present invention relates to a semiconductor memory device. More particularly, the present invention relates to a method for fabricating a memory device wherein a guard contact formed in a chip guard is strengthened to prevent cracking caused from outside stresses. [0003] FIG. 1 is a layout view illustrating a conventional semiconductor device. FIG. 2 is a simplified cross-sectional view taken along line I-I′ of FIG. 1 . [0004] Referring to FIGS. 1 and 2 , a lower electrode line structure 30 and an upper electrode line structure 50 are disposed over a semiconductor substrate (not shown) having a lower structure including a gate, a bit line, and a bit line contact. A guard contact 40 is disposed between the lower electrode line structure 30 and the upper electrode line structure 50 . Here, the guard contact 40 is formed of a whole body-type contact vertical to the lower electrode line structure 30 . The guard contact 40 is formed to prevent impurity particles from passing. [0005] FIG. 3 is a simplified cross-sectional view illustrating a conventional semiconductor device. In particular, it shows the failure of a fuse guard structure caused by the outside stresses. [0006] Referring to FIG. 3 , a gate 5 and a bit line 20 is formed over a semiconductor substrate (not shown), and a bit line contact 15 is formed to connect the bit line 20 to the gate 5 . A lower electrode line structure 30 is formed over the bit line 20 , and a lower electrode contact 25 is formed to connect the lower electrode line structure 30 to the bit line 20 . An upper electrode line structure 50 is formed over the lower electrode line structure 30 , and a whole body-type guard contact 40 is formed to connect the upper electrode line structure 50 to the lower electrode line structure 30 . [0007] According to the above conventional semiconductor device, the guard contact cannot prevent a crack from occurring when a chip is cut due to shrinkage to a fuse of the device. As a result, a “cracking phenomenon” between the electrode line structures shown in FIG. 3 occurs due to the outside stress and pressures in other processes. This allows impurity particles to enter into the lower electrode line structure through the cracks. Accordingly, the yield and reliability of the device may be degraded. BRIEF SUMMARY OF THE INVENTION [0008] The present invention relates to a semiconductor device and a method for fabricating wherein a guard contact formed in a chip guard is designed with two portions with different line widths. The two portions provide a zigzag or criss-cross pattern to increase the strength of the structure, thereby preventing impurity particles from passing and increasing resistance against outside stresses. Accordingly, reliability and yield of the device can be improved. [0009] According to an embodiment of the present invention, a semiconductor device having an upper electrode line structure and a lower electrode line structure over a semiconductor substrate includes: a guard contact having a first portion and a second portion with different line width, disposed between the upper electrode line structure and the lower electrode line structure, wherein the first portion is disposed parallel to the upper electrode line structure, and the second portion is disposed perpendicular to the upper electrode line structure. [0010] According to another embodiment of the present invention, a method for fabricating a semiconductor device includes: (a) forming a lower electrode line structure over a semiconductor substrate having a lower structure; (b) forming a guard line having a first portion and a second portion over the lower electrode structure, wherein the line width of the first and second regions are different; and (c) forming an upper electrode line structure over the guard contact. BRIEF DESCRIPTION OF THE DRAWINGS [0011] FIG. 1 is a simplified layout of a conventional semiconductor device. [0012] FIG. 2 is a simplified cross-sectional view illustrating a conventional semiconductor device. [0013] FIG. 3 is a simplified cross-sectional view illustrating a conventional semiconductor device. [0014] FIG. 4 is a simplified layout of a semiconductor device according to one embodiment of the present invention. [0015] FIG. 5 is a simplified cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [0016] FIG. 6 is a simplified layout of a semiconductor device according to another embodiment of the present invention. DESCRIPTION OF SPECIFIC EMBODIMENTS [0017] FIG. 4 is a simplified layout of a semiconductor device according to one embodiment of the present invention. A lower electrode line structure 130 and an upper electrode line structure 150 are manufactured parallel to each other over a semiconductor substrate (not shown) having a lower structure (not shown). A guard contact 140 having a first portion 145 and a second portion 143 with different line widths are disposed between the lower electrode line structure 130 and the upper electrode line structure 150 . [0018] In one embodiment of the present invention, the first portion 145 and the second portion 143 of the guard contact 140 are alternately disposed over the lower electrode line structure 130 in a zigzag pattern, as can be seen in FIG. 4 a . In addition, the line width of the second portion 143 (B) is equal to or greater than that of the first portion 145 (A). In one implementation, the line width of the second portion 143 is at least twice that of the first portion 145 , the width being the direction along the longitudinal extension of the lower electrode line structure 130 . [0019] FIG. 5 is a simplified cross-sectional view taken along the line II-II′ of FIG. 4 . Reference symbols A and B denote the line width of the first portion 145 and that of the second portion 143 , respectively. Since B is greater than A in the guard contact 140 , the lower electrode line structure 130 can support the outside stress or pressure from other processes, thereby preventing cracking phenomenon for the guard contact. Thereafter, an upper electrode line structure 150 is formed over the guard contact 140 . [0020] FIG. 6 is a simplified layout of a semiconductor device according to another embodiment of the present invention. A lower electrode line structure 130 and an upper electrode line structure 150 are manufactured parallel to each other over the semiconductor substrate (not shown). A guard contact 140 having a first portion 145 and a second portion 143 with different line widths is disposed between the lower electrode line structure 130 and the upper electrode line structure 150 . [0021] In another embodiment of the present invention, the first portion 145 and the second portion 143 of the guard contact 140 are alternately disposed over the lower electrode line structure 130 , where the two portions (or regions) are centered over the lower electrode line structure 130 , as can be seen in FIG. 6 . The second portion 143 has substantially the same line width along a longitudinal direction of the lower electrode line structure 130 . In addition, the line width of the second portion 143 (B) is greater than that of the first portion 145 (A). [0022] According to one embodiment of the present invention, since the guard contact plays the role of a structural member for supporting the outside stresses or pressures, the electrode line structures are prevented from cracking and allowing impurity particles to enter the electrode line structures. Accordingly, the process yield and reliability of the device can be improved. [0023] The description of various embodiments of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and modifications and variations are possible in light of the above teachings. The embodiments were chosen and described in order to explain the principles of the invention and its practical application to enable one skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use.

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Patent Citations (10)

    Publication numberPublication dateAssigneeTitle
    US-2003218254-A1November 27, 2003Matsushita Electric Industrial Co., Ltd.Semiconductor device and manufacturing method thereof
    US-2004217477-A1November 04, 2004Taiwan Semiconductor Manufacturing CompanyRF seal ring structure
    US-2005098893-A1May 12, 2005Matsushita Electric Industrial Co., Ltd.Semiconductor device and method for fabricating the same
    US-5270256-ADecember 14, 1993Intel CorporationMethod of forming a guard wall to reduce delamination effects
    US-5674787-AOctober 07, 1997Sematech, Inc.Selective electroless copper deposited interconnect plugs for ULSI applications
    US-5834829-ANovember 10, 1998International Business Machines Corporation, Siemens Components, Inc.Energy relieving crack stop
    US-6022791-AFebruary 08, 2000International Business Machines CorporationChip crack stop
    US-6163065-ADecember 19, 2000Intel CorporationEnergy-absorbing stable guard ring
    US-6365958-B1April 02, 2002Texas Instruments IncorporatedSacrificial structures for arresting insulator cracks in semiconductor devices
    US-6495918-B1December 17, 2002Infineon Technologies Ag, International Business Machines CorporationChip crack stop design for semiconductor chips

NO-Patent Citations (0)

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    Publication numberPublication dateAssigneeTitle